[Day01] 有時候學硬體或者設計硬體累了…來點軟體吧!

前言 雖然我正在Mediatek實習,待的部門是做手機CPU的部門,不是RTL designer 是做 Implement team的。其實心中預期比較多的是實習能碰Implement 因為在學校其實沒甚麼機會走到PnR, Sign-off等等後端真正的流程。大多是RTL打一打,丟進工具與幾個library隨便合成後跑跑Netlist sim就完工了。一部分是因為走完這些的時間就不太夠了更不太可能在學校上課的期間能走到GDS Tapout。但我發現每天看standard cell、每天看數位電路其實也蠻膩的。於是大膽下定決心累的時候除了運動,可以多練習軟實力。如果以後數位設計失業至少還能寫code維生xD 軟體要來學點甚麼? 我之前聽了一個CS部門的同事分享,雖然資料結構、作業系統和演算法甚麼得很重要,但說真的他最受用無窮的就是軟體設計模式(software design pattern)。那時候在台下的我覺得很有道理,Design pattern似乎是一個放諸四海皆準的一個主題,可以幫助你在專案中的coding style等更一致更有準則,容易解釋容易讓人參與其中。所以我就決定在設計Risc v的閒餘時間多學習設計模式。當然這也算是side project另外一個Side project xD 目前就陳列一下side project: LiteX on iCE-sugarpro E203 Risc-V re-implement combine opensource skywater 130nm pdk(?)或許可以搭Google的車Tapeout,等學到一定程度就到openIC study group上號召XD Software design pattern 廢話不多說,我是在網路上找到一個IT鐵人賽,教你學設計模式 [ Day 1 ] 我為什麼想學設計模式 ( Design Pattern ) 但是我應該會想用C/C++來寫這個課題,而這位大神是使用Java。

[Day16] RISC-V open hardware design

What is the difference between RISC and CISC? CISC (Complex-Instrument-Set-Computer) is an instrument set that contains common instruments and uncommon instruments. For example, 80% of the common instruments we used in the arithmetic program is 20% of the total instrument set. RISC (Reduced-Instrument-Set-Computer) only contains common instruments.

[Day15] Linux on LiteX - iCESugar-Pro

Install icesprog icesprog is a tool which can program FPGA. https://github.com/FPGAwars/toolchain-icesprog sudo apt install git && git clone https://github.com/FPGAwars/toolchain-icesprog.git cd toolchain-icesprog ./build.sh linux_i686 ./build.sh linux_x86_64 ./build.sh windows_x86 ./build.sh windows_amd64 In my WSL setup, run ./build.sh windows_amd64 and restart command line tool. Type icesprog.

[Day14] COSCUP waxapple wandering

Skywater 130nm PDK OSS eFabless OpenLane One push button to start your ASIC design! Share note The efabless Caravel project—Chip design for the software-oriented - Tim Edwards, Mohamed Shalan tags: COSCUP2021 Skilled en COSCUP2021 Bringing Open Source Software to Hardware TR313 {%hackmd kra72OaxRTiBzdV8Y4GMKA %}

[Day13] Writing a simple state machine

What is missing? Actually, when I am writing this article, there is not much tutorial on nmigen. It is not complete in nmigen tutorial. In this tutorial, I will try my best to elaborate a FSM circuit. Finite state machine Let’s say… I want a circuit which samples data every 128+1 clock cycles.