Supported devices See the vendor directory for supported devices and toolchain details.
Devices supported as of 18 JUL 2021:
Device Platform Toolchain required Lattice iCE40 Yosys+nextpnr, LSE-iCECube2, Synplify-iCECube2 Lattice MachXO2 Diamond Lattice ECP5 Yosys+nextpnr, Diamond Xilinx Spartan 3A Xilinx ISE Xilinx Spartan 6 Xilinx ISE Xilinx 7-series (Arty, Spartan, Kintex, Virtex) Xilinx Vivado Xilinx UltraScale XilinxUltraScalePlatform Vivado Intel IntelPlatform Quartus Defining your board Many boards are defined for you at nmigen_boards.
Simulating The best way to simulate a module is through nMigen’s Simulator.
Define you ports Define a ports function in your module which returns an array of your module’s ports:
1 2 3 4 class YourModule(Elaboratable): ... def ports(self): return [self.youmodule.p1, self.
Spliting and combining signals Slicing signals We can get the least significant bit by x[0] or the most significant bit by x[15].
1 2 3 4 5 6 7 8 9 10 >>> from nmigen import * >>> x = Signal(16) >>> x (sig x) >>> x.
If-Elif-Else you cannot use the standard python if-elif-else statements to create statements. Instead, using nMigen branching.
1 2 3 4 5 6 with m.If(condition1): m.d.comb += statements1 with m.Elif(condition2): m.d.comb += statements2 with m.Else(): m.d.comb += statements3 If you use regular Python if-elif-else, then those will be evaluated during generation of the logic, not the logic itself.