Basic structure of modules

The tutorial is followed by https://github.com/RobertBaruch/nmigen-tutorial/ Thumbs up for his contributions.

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from nmigen import *
from nmigen.build import Platform

class ThingBlock(Elaboratable):
    def __init__(self):
        pass
    def elaborate(self, platform: Platform) -> Module:
        m = Module()
        return m

Elaborating a module

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from nmigen.cli import main

if __name__== "__main__":
    sync = ClockDomain()
    block = ThingBlock()

    m = Module()
    m.domains += sync
    m.submodules += block

    main(m, ports=[sync.clk,sync.rst])

• main(module, ports=[], platform="") translate the given module into verilog. This is call elaboration. All elaborate() medthod will have its platform argument set to the given platform like particular chips or evaluation boards.

python3 thing.py generate -t [v|il] > thing.[v|il]

If you encounter any error message, Back to day00 and install the pre-requisties.

• Choose RTLIL if using yosys.