If-Elif-Else
you cannot use the standard python if-elif-else
statements to create statements. Instead, using nMigen branching.
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If you use regular Python if-elif-else
, then those will be evaluated during generation of the logic, not the logic itself. This can be useful if you want a flag to cause different logic implement to be generated, and this is a good use of platform string pass to elaborate().
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If platform
is "KC705"
then statement1 will be implement in generated hardware, otherwise only statement2 will be implement in the design.
Conditions
The conditions in If-Elif-Else
are cimparisons, for example a == 1
or (a >= b) & (a <= c)
. Note that each comparison will be one-bit comparison.
If you have a signal with more than one bit and use it as the condition, use with m.If(a):
, then the condition will be true if any bit in a is 1.
Switch-Case-Default
You can use Switch-Case-Default
just as in standard HDLs using the following with
constructs:
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Although it is suggested that using full-case
switch that we used to do in verilog. You can use multiple values in one case statement.
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You can leave out the Defalt()
, but not suggest you to do that.
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In this example, if y is in [0, 1, 2]
then x
is assigned 2. Otherwise x
retains its value of 1.
- Recall the section on overriding statements. One signal can only assigned in only one clock domain.
Specify a bit patterns
The way to specify a matching pattern in a Case
is with a Python string of binary digits. For example, "0011101011"
. A don’t-care bit is specified using a dash -
, so for example "00111-----"
. The number of bits in the string must exactly the same as the number of bits in the expression it is being compared to.
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Is equivelent to
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