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from typing import List

from nmigen import Elaboratable, Module, Signal
from nmigen.back.pysim import Simulator, Delay
from nmigen.build import Platform
from nmigen.cli import main_parser, main_runner

class Adder(Elaboratable):
    def __init__(self):
        self.x = Signal(8)
        self.y = Signal(8)
        self.out = Signal(8)

    def elaborate(self, paltform: Platform) -> Module:
        m = Module()

        m.d.comb += self.out.eq(self.x + self.y)
        return m 
    def ports(self) -> List[Signal]:
        return [self.x, self.y, self.out]
if __name__ == "__main__":
    parser = main_parser()
    args = parser.parse_args()
    m = Module()
    
    m.submodules.adder = adder = Adder()
    
    # main_runner(parser, args, m, ports=[] + adder.ports())
    x = Signal(8)
    y = Signal(8)
    m.d.comb += adder.x.eq(x)
    m.d.comb += adder.y.eq(y)
    sim = Simulator(m)
    def process():
        yield x.eq(0x00)
        yield y.eq(0x00)
        yield Delay(1e-6)
        yield x.eq(0xFF)
        yield y.eq(0xFF)
        yield Delay(1e-6)
        yield x.eq(0x00)
        yield Delay(1e-6)
    sim.add_process(process)
    with sim.write_vcd("test.vcd", "test.gtkw", traces=[x, y] + adder.ports()):
        sim.run()
    print("end of code")